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AI is scaling to domains of ten thousand accelerators, and the interconnect has to keep up. We’re building it at the intersection of photonics, semiconductors and large-scale computing.
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CMOS/Electrical Chip
04Laser
03Packaging & Ops
08- Advanced Packaging Engineer — Fiber Array Integration Palo Alto, CA
- Advanced Packaging Engineer — Fiber Array Integration Shanghai
- FEA Packaging Engineer Palo Alto, CA
- Package Design & Layout Engineer Palo Alto, CA
- Package Design & Layout Engineer Shanghai
- Package Design & Layout Engineer Taiwan
- Package Mechanical FEA Engineer Palo Alto, CA
- Thermal Simulation Engineer Palo Alto, CA